1. Field of the Invention
The present disclosure generally relates to the field of computer systems, and, in particular, to systems comprising a plurality of processors.
2. Description of the Related Art
In modern computer systems, processors are employed which comprise a plurality of instructions. The processor reads instructions and data from a system memory connected to the processor, and modifies the instructions and/or data in accordance with the instructions. The system memory may comprise volatile, but quickly accessible, memory devices, such as RAMs, as well as slow, but permanent, memory devices, such as hard disks. Moreover, the computer may receive input from devices such as a keyboard, a mouse and/or a network connection, and may provide output to devices such as, e.g., a monitor, one or more loud-speakers and/or a printer. In most computer systems, a specialized computer program, which is denoted as the “operating system,” is employed to control the processing of various programs as well as the transfer of data between the components of the computer system.
FIG. 1a shows a schematic block diagram of a computer system 100 according to the state of the art. The computer system 100 comprises a processor 101, a system memory 104 and one or more input/output devices 103. Arrows 102 schematically indicate the transfer of data between the processor 101, the system memory 104 and the input/output device(s) 103.
The processor 101 comprises a plurality of registers 102, 103, 104, 105. Data may be read from the system memory 104 into the registers 102-105, and data in the registers 102-105 may be written to the system memory 104. The processor 101 may comprise instructions adapted to modify the contents of the registers 102-105, as well as instructions to transfer data between the registers 102-105 and the system memory 104 and/or between the registers 102-105. Moreover, instructions which perform a combination of such tasks may be provided. Typically, the processor 101 may access data in the registers 102-105 much faster than data stored in the system memory 104.
In order to improve the performance of the computer system 100, it may be desirable to provide a plurality of processors, instead of one single processor 101. Thus, a plurality of tasks and/or threads may be executed simultaneously. This may help increase the speed of operation of the computer system 100.
In computer systems according to the state of the art, however, an increase of the number of processors may require a modification of the operating system, as will be explained in the following with reference to FIG. 1b. FIG. 1b shows a schematic flow diagram of a task 201 running on the processor 101 in the computer system 100 according to the state of the art. The task 201 comprises a plurality of instructions 210-215 which are to be processed sequentially by the processor 101. Hence, the processor 101 proceeds from instruction 210 to instruction 211, and from instruction 211 to instruction 212.
While the task 201 is processed, for example, during or after the processing of instruction 212, an interrupt or exception may occur, which is indicated schematically by arrow 230 in FIG. 1b. An exception may be generated in case of an error during the processing of instruction 212, for example, in case of a division by zero or in case of an error message from the system memory 104, such as a page fault. Exceptions may also be generated regularly by instructions of the task 201, for example, by instruction 212. A typical application of an exception generated by the task 201 is a call of the operating system of the computer system 100. Interrupts may be generated by events originating from devices other than the processor 101, for example, by input into the input/output device 103, or by a synchronization request of the input/output device 103. If multitasking is performed in the computer system 100, interrupts generated by a timing circuit may be employed to alternately activate the various tasks, which may be processes or threads.
In case of an interrupt or exception, the execution of the task 201 may be interrupted and an interrupt routine 202, which may, for example, be part of the operating system, is executed. The interrupt routine 202 comprises a plurality of instructions 220-225. These instructions are processed sequentially. After processing the last instruction 225 of the interrupt routine 202, processing of the task 201 is continued at the instruction following the instruction 212 at which the interrupt occurred, i.e., in the above example, at instruction 213.
The interrupt routine 202 may modify the content of the registers 102-105 of the processor 101. In order to insure that the task 201 will function properly in spite of the interrupt or exception, after the occurrence of the interrupt or exception, the content of the registers 102-105 is copied to a storage location in the system memory 104. Before the execution of the task 201 is continued, the content of the storage location is read back into the registers 102-105. Thus, when the execution of the task 201 is continued by executing the instruction 213, the registers 102-105 may comprise substantially the same data as if the instruction 213 would have been executed immediately after instruction 212.
In computer systems 100 according to the state of the art, copying of the content of the register to the storage location and back is effected by instructions provided in the interrupt routine 202, which are implemented as part of the operating system of the computer system 100. Hence, in case additional processors are provided in the computer system 100, modifications of the operating system may be required to insure that, in the event of an interrupt or exception occurring in any of the processors, the content of the registers of the processors is correctly stored in the system memory and read back into the registers after the completion of the interrupt routine.
Further modifications of the operating system may be required in order to schedule the execution of processes and tasks in the individual processors. In computer systems according to the state of the art, the control of the execution of the processes and/or threads in the processors and the distribution of programs and/or threads to the processors is performed by the operating system. In addition to requiring an adaptation of the operating system to the presence of a plurality of processors, the control of the execution of processes and/or thread may require a relatively large overhead for the creation and/or control of processes and/or threads. In particular, a considerable overhead may be created by copying the contents of registers of the processors to a storage location before an operating system routine is called, and reading the content of the storage location back into the registers after the termination of the operating system routine.
A problem of the computer system 100 according to the state of the art is that additional processors provided in the computer system 100 may not reasonably be used until manufacturers of operating systems implement support for the additional processors or any other possible devices.
A further problem of the computer system 100 according to the state of the art is that a relatively large overhead for the creation and/or control of processes and/or threads by means of the operating system may reduce the performance of the computer system 100, in particular, if relatively fine grain multitasking and/or multithreading is used.
Furthermore, even in computer systems according to the state of the art providing support for multiple processors, it may be desirable to hide additional processors or features from the operating system. This also might include additional hardware and/or processors which are not known to the operating system. Hence, a further problem of computer systems according to the state of the art is that it may be hard to use additional resources such as processors or hardware which are not visible to the operating system.
The present disclosure is directed to various systems and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.